CMOS图像传感器的四通道扩展计数ADC设计

A 4-channel extended counting ADC for CMOS image sensor readout

面向科研领域应用的CMOS图像传感器，需要具有低噪声、高动态范围和高灰度分辨率的特点.本文分析了多通道扩展计数ADC结构的性能，提出了一种基于相关多采样技术(Correlated Multiple Sampling, CMS)的15位四通道扩展计数ADC.该ADC的4个并行输入通道采用增量型ADC，第二级采用1个循环型ADC在通道间复用.ADC电路基于0.11μm CMOS工艺进行设计，仿真结果显示，在128次多采样下，ADC的分辨率为15位，信号信噪比可提高9.22 dB，此时积分非线性(INL)和微分非线性(DNL)分别为-3.32 LSB和-2.58 LSB，4通道最高采样率为133 KSPS，在3.3 V电源电压下，平均每通道功耗为650 μW.

Abstract: A 15-bit 4-channel extended counting (EC) ADC with correlated multiple sampling (CMS) is designed for low-noise column readout in scientific CMOS image sensors (CISs). The 4-channel EC ADC structure is composed of 4 Incremental ΔΣ ADCs (IADCs) working in parallel and a cyclic ADC to increase the readout speed. The ADC is designed and implemented in a 0.11 μm CMOS process. The readout speed of the 4-channel EC ADC is 133KSPS at 5MHz clock frequency. Simulation results show that the maximum INL and DNL of the ADC with 128 times multiple sampling are -3.32 and -2.58 LSBs, and the CMS brings forth a 9.22 dB improvement in SNR. The power consumption is 650 μW per channel at 3.3 V supply voltage.