Abstract: In order to meet more application scenarios, intelligent sensing devices have to face the challenges of computing power and power consumption. This work proposes a CIM architecture that supports multi-layer and multi-bit. Balance the need for high computing power and low power consumption. The CIM unit in this architecture has its own performance advantages, not only supporting the integration of the architecture, but also achieving better system performance. This CIM unit circuit proposes a CIM unit based on the standard 6T-SRAM, four transistors and a Metal-Oxide-Metal (MOM) capacitor. The MOM capacitor is shared with the capacitor in SAR ADC. This method saves power consumption and area. Multiply-And-Accumulate (MAC) computation of signed number is realized in charge domain. The ResNet14 network is deployed in the CIM architecture, this work can achieve calculations of 1 bit weight, 4 bit activation (1w4a) and 4 bit weight, 4 bit activation (4w4a). The design is implemented using 40 nm CMOS technology, with on-chip memory of 576 KB, achieving a pre-simulation energy efficiency of 353.2 TOPS/W and a throughput rate of 716.308 GOPS at a working frequency of 10 MHz.