Abstract: Traditional low density parity check codes (LDPC) perform poorly in low signal-to-noise ratio environments, the low density parity check Hadamard code (Hadamard-LDPC) is considered to be a new type of ultimate-Shannon-limit-approaching code. The traditional Hadamard-LDPC decoder exploits the symbol-maximum-a-posteriori probability (Symbol-MAP) rule which introduces logarithmic and exponential operations, leading to high computational complexity and high resources occupation, which is not conducive to the implementation of engineering applications. This paper proposes a Max-log-MAP rule-based layered normalized QC-Hadamard-LDPC decoding algorithm which utilizes additive and comparison operations instead of non-linear ones so that the decoding complexity can be efficiently reduced. To further cope with the performance degradation and extrinsic information distortion caused by the introduced linear computations, a normalization factor is introduced and optimized in terms of the bit error rate (BER) performance. The entire system is implemented on an FPGA board. A bit error rate of 10⁻⁵ can be achieved at E_b/N₀ = 0.4 dB with a moderate message bits length 1024 and a throughput of 313 Mbps. The layered decoder using 20 decoding iterations shows twenty percent decrease of resource utilization at a slight sacrifice of a very small degradation of 0.03 dB, compared with the standard decoder.