Abstract: A 14-bit successive approximation Analog-to-Digital converter (SAR ADC) for Internet of Things (IoT) applications, designed using the 180 nm CMOS process, is introduced. The capacitor array employs segmentation and redundancy techniques, adding two redundant capacitors in the high-segment capacitor, which improves the accuracy and linearity of the ADC while reducing the layout area. To achieve high precision, a dynamic comparator using a charge pump-based offset voltage reduction technique is implemented. The successive approximation comparison loop based on the charge pump alters the substrate voltage difference of the two input transistors of the fully dynamic preamplifier, effectively compensating for the offset voltage and ultimately stabilizing within a small offset step. Compared to a traditional static preamplifier, the fully dynamic preamplifier saves more power consumption. Compared to existing charge pump compensation techniques, it uses simpler calibration logic, significantly reducing the cost of digital circuits. Dynamic Element Matching (DEM) technology is used to improve the matching of the top three bits of capacitance in the capacitor array. The top three bits of capacitance are split into seven equal-sized capacitors, allowing for equal probability of selection during the capacitance conversion process. This averages out the error due to capacitor mismatch, thereby distributing the harmonics evenly across the frequency domain to minimize the impact of capacitor mismatch. Simulation results show that at a sampling frequency of 4 kS/s and a supply voltage of 1.8 V, the Spurious-Free Dynamic Range(SFDR) is 94.9 dB, power consumption is 1.002 μW, and the ENOB of bits is 13.01 bit.