Abstract: To reduce the on-resistance and its flatness of conventional CMOS analog switches, this paper proposes a circuit design method employing dual-ended floating substrate potential, which addresses the issues of increased on-resistance and degraded flatness caused by threshold voltage variations due to the substrate bias effect. Based on the proposed switch structure, a low on-resistance 8-to-1 high-voltage analog switch circuit is designed using a 0.5-μm high-voltage BCD process. Simulation verification is conducted under a dual supply voltage of ±5 V with an input signal range of −3 V to 3 V. The results demonstrate that the minimum on-resistance of a single-channel analog switch reaches 12.55 Ω, with a flatness of 2.68 Ω, satisfying the design requirements of low on-resistance and high flatness, and effectively reducing signal loss and transmission delay. Furthermore, the circuit is compatible with TTL/CMOS logic inputs, supports either dual or single supply voltages, and operates over the full VDD-to-VSS supply range, while integrating enable control and ESD protection functions. Simulation results for key performance metrics are favorable, indicating that the proposed design exhibits good feasibility and engineering value in practical applications.