Abstract: Lateral Double-diffused complementary Metal Oxide Semiconductor(LDMOS) devices have the characteristics of extremely high switching speed, strong driving ability, high input impedance, and high thermal stability. LDMOS devices are mainly applied in intelligent power integrated circuits and are also the mainstream power devices in the BCD process. The current research hotpots on LDMOS devices concentrate mainly on the optimization of their structures, especially focusing on how to balance the contradictory optimization parameters of breakdown voltage and specific on resistance. In order to balance these two parameters to obtain LDMOS devices with higher performance, various performance optimization methods have been proposed. Introducing the multi-gate structure into LDMOS devices as an effective performance improvement method has its unique advantages, but there are relatively few related studies. The optimization of multi gate structures in LDMOS devices reported in recent years are mainly focused on, and the influence of multi gate for the performance of LDMOS devices are analyzing. The role and effect of double gate, planner gate, trench gate, drift region gate, and triple gate in the improvement of LDMOS devices are discussed in detail. Finally, the advantages and disadvantages of these optimized structures compared with traditional structures are summarized.