Abstract: EDAC (Error Detection and Correction) combining with bit-interleaving is the domestic single-event upset hardening method for the large-capacity on-chip memories, widely used in advanced microprocessors for harsh environments. Based on the high LET heavy ion radiation test, the single-event upset effect is studied in the EDAC and bit-interleaving hardened storage systems of a multicore microprocessor. The mechanism of the SEU is found for the first time, which is attributed to the influence of multi-bits upsets caused by multiple heavy ions on the same logical address. A compact model of the SEU cross-section is proposed for the SEC-DED (Single Error Correct/Double Error Detect) and bit-interleaving hardening storage system, which is consistent with the test results. Reducing the SRAM refresh period and the EDAC bit width data can enhance the MBU resistance of the EDAC and bit interleaving hardening method.