Abstract: An R-C hybrid SAR ADC with excellent monotonicity is proposed, in which the high-eight-bit digital-to-analog converter adopts a resistive structure, and the low-four-bit DAC adopts a capacitive structure. The reference voltage is divided equally through the resistive divider in the high-eight-bit DAC, and the voltage closest to the input sampling signal is selected as the output of high-eight-bit DAC. Then the result is input to the low-four-bit capacitive DAC for charge redistribution process, and finally the 12-bit DAC output is realized. In order to reduce the error caused by process mismatch, the lower-four-bit capacitive DAC consists of only two capacitors with a ratio of 15C: C. The 15C-capacitor is connected to the output of the high-eight-bit resistive DAC, which is affected by the high-eight-bit control signal D11:4.The voltage connected to the C-capacitor is also output by the high-eight-bit resistive DAC, which is affected by both the high-eight-bit and the low-four-bit control signal D11:0. Since the input voltage of the low-four-bit capacitive DAC is only correlated with the output voltage of the high-eight-bit resistive DAC, and the resistive DAC has good monotonicity, it is only necessary to ensure that the 15C-capacitor and C-capacitor in the low-four-bit DAC are well matched to achieve good monotonicity. At the same time, the ADC is compatible with both differential and single-ended input modes. The proposed ADC is implemented using GRACE 0.11 μm CMOS process, the post-simulation results show that the differential nonlinearity and integral nonlinearity are both less than ±1 LSB in all the process corners and temperature environments. The ENOB is 11.4 bit under typical conditions, and the maximum power consumption is smaller than 600 μA, which can be suitable for medium- and high-precision and low-cost applications.