Abstract: Fast Fourier transform (FFT) technology is widely used in the fields of filtering, communication and digital spectrum analysis. In order to realize the hardware acceleration of FFT, this paper first studies the principle of FFT algorithm. The research is based on the symmetry, periodicity and reducibility of rotation factor in Discrete Fourier Transform. The focus of the research is the decomposition and extraction from long sequence Discrete Fourier Transform to short sequence Discrete Fourier Transform. Four typical FFT acceleration engine hardware architectures are further studied, including sequential processing architecture, pipeline architecture, parallel iterative architecture and array architecture. Taking into account computational speed, complexity of data scheduling, and resource overhead, this paper adopts a pipeline architecture. In single delay feedback structure, the output of the butterfly operation unit and the complex multiplication unit may conflict. Therefore, this article proposes a 13-stage hybrid pipelined architecture which combines 9-stage single-path delay feedback + 4-stage multi-path delay commutator. The FFT acceleration engine designed in this article is implemented in 65 nm process and 28 nm process respectively. The maximum operating frequency is 1 GHz and the computing performance reaches 260 Gflops.