Abstract: With the development of the RISC-V architecture ecosystem in recent years, processors based on the RISC-V architecture have been increasingly used in the aerospace field in Europe and the United States, but there are currently no reported RISC-V architecture processor products for aerospace use in China. Due to the large amount of high-energy radiation in the working environment of aerospace processors, single event upset will occur in the devices inside the processor, which will lead to errors in the execution results of the processor. To solve the above problems, a self-developed low-power RISC-V architecture processor is hardened against single event upset. In view of the characteristics of the RISC-V architecture, the pipeline non-traceable registers are hardened with triple modular redundancy, and the traceable registers are hardened by combining error detection and instruction traceback technology; at the same time, the register files were hardened by combining error detection and correction (EDAC) technology and checkpoint and rollback recovery (CRR) technology. The additional hardware overhead brought by the hardening is reduced by 47% compared to the common hardening method that only uses triple modular redundancy. Based on the hardened RISC-V processor, an aerospace MCU product is implemented, and single event upset experiments prove that the hardened processor can correct 98.3% of single event upset errors, laying the foundation for the application of RISC-V architecture processors in the domestic aerospace field.