Abstract: The mode selection mechanism specified in the LC3plus (Low Complexity Communication Codec plus) protocol is used to support the adaptive selection of the optimal packet loss concealment technique in audio decoders. This part involves complex mathematical operations and extensive data read and write processes, which increase computation delays in the CPU. This paper proposes a hardware architecture to coordinate the internal data interactions of the mode selection mechanism, significantly reducing the logical resource consumption by reusing the computation units. The selection module implemented in this work has undergone functional simulation and FPGA verification. The test results demonstrate that the designed hardware module meets the requirements of the LC3plus protocol and achieves significant processing acceleration with minimal hardware overhead.