• 低抖动8 GHz高速时钟驱动器的设计

    Design of a low jitter, 8 GHz high speed clock driver

    • 针对先进电子系统对高速度、低抖动、低通道偏斜系统时钟的应用需求,基于0.18 μm SiGe BiCMOS工艺设计了一种同时提供两路时钟输出的高速时钟驱动器。其内部集成了带隙基准、输入缓冲器、输出放大器、射极输出等功能模块。其中,输入缓冲器电路采用有源反馈技术,在提高电路增益的同时实现了带宽拓展;输出放大器通过电容峰值技术在电路中引入零点补偿极点的方法显著拓展了电路带宽。测试结果表明:设计的时钟驱动器在电源电压3.0 ~ 3.6 V、工作温度−55℃ ~ 125 ℃的条件下,最高工作频率均不小于8 GHz,附加抖动低至21.16 fs(@622.88 MHz,积分区间12 kHz ~ 20 MHz),通道间偏斜不大于10 ps。该时钟驱动器可以为系统同时提供两路高速度、高稳定度的时钟信号,可应用于通信系统、高性能计算、电子战等各种先进电子系统中。

       

      Abstract: In order to meet the demand of high speed, low jitter and low skew system clocks for advanced electronic systems, a high speed clock driver with two outputs is proposed in this paper. The proposed clock driver is mainly composed of modules such as bandgap reference, input buffer, output amplifier and so on. The active feedback skill are adopted to increase gain and expand bandwidth in the input buffer. The output amplifier introduces the method of zero compensation pole by the capacitor peaking skill, which significantly expands the bandwidth of the output amplifier. This high speed clock driver is realized in 0.18 μm SiGe BiCMOS process. The test results show that the maximum operating frequency of this design is not less than 8 GHz under the condition of power voltage between 3.0 V and 3.6 V, operating temperature between −55 ℃ and 125 ℃. In addition, the random additive jitter is 21.16 fs @ 622.88 MHz when integrated from 12 kHz to 20 MHz. The skew between two outputs is less than 10 ps. This clock driver can provide two high speed and high stability clock outputs for at the same time. It has been popularly used in various advanced electronic systems such as communication systems, high performance computing, electronic warfare and so on.

       

    /

    返回文章
    返回