Abstract: In IC physical design, it is an important guarantee for faster and more efficient timing convergence and timing consistency before and after design to accurately extract and calculate the RC parameters in the circuit. In the physical design of digital IC, due to the large difference of RC parasitic parameters extracted by different tools, the timing consistency before and after design cannot be guaranteed. In this paper, an auxiliary tool Ostrich is proposed to compare SPEF files from different sources, so as to generate scaling factors to calibrate RC parameters and further modify the design. Finally, through the project verification, the fit of WNS and TNS with the signing standard has been improved, which proves that the method can effectively improve the reliability of the system and achieve the purpose of timing consistency before and after the design.