Abstract: Due to the high requirement for reporting rate of capacitive touch chips, generally greater than 120 Hz, multiple ADCs need to be built in for real-time sampling. A Small Area Successive approximation Analog-to-Digital Converter (SAR ADC) with 3.3 V power supply, 8 MS/s sampling rate, and 14 bit accuracy has been designed for capacitive touch applications. This design uses a gate voltage bootstrap switch to achieve 14 bit high-precision sampling. In the strategy of reducing chip area, a proportional benchmark two-step DAC (Digital to Analog Converter) is used to achieve a 14 bit ADC with only a 7 bit capacitor DAC, effectively reducing the area. This design also adopts a dynamic comparator with three-stage cascaded preamplifiers, which has the advantages of fast speed and low power consumption, and can effectively reduce input offset voltage and noise. In the sample and hold circuit section, this design adopts a CMOS fully differential sample and hold circuit, which can handle a wide range of input common mode signals with a small area and low noise. The ADC design in this article adopts a 180 nm 1P4M CMOS process, achieving a signal-to-noise distortion ratio of 14 conversion bits, effective bits of 11.84, and 74.03 dB. The power consumption under 3.3 V power supply is 500.9 μW, and the area is 0.16 mm².