Abstract: The aim of this study is to validate the implementation of a digital domain correction method on hardware with basis of the FastICA algorithm. This algorithm compensates for I/Q imbalance by separating independent components from mixed signals, while introducing differential thinking to adjust correction parameters in real-time to adapt to the processing of streaming signals. The effectiveness of the proposed algorithm is verified through simulation and hardware testing. The results show that, under 1 MHz single tone signal input and 100 MHz sampling frequency, after correction, the image suppression ratio increase from 13.5 dB to 55.8 dB, and in hardware testing, it increases to 51.4 dB. It can be seen that the image suppression module designed in this study can effectively suppress DC offset and image interference, improve the performance of zero IF transceivers, and confirm an effective I/Q imbalance correction method.