• 一种用于音频编解码器的高精度Delta-Sigma调制器

    A high precision Delta-Sigma modulator for audio codec

    • 面向音频编解码器设计了一款高精度Delta-Sigma调制器。采用具有高输入动态范围特性的CIFF架构,环路滤波器设计为3阶单环结构,并结合4位量化器以降低高阶系统的开关电容积分器过载概率,同时进一步提高信噪失真比。采用了可编程增益放大器(programmable Gain Amplifier, PGA)作为Delta-Sigma调制器的输入级,PGA在小幅度信号输入情况下可放大输入信号,提高调制器的动态范围;采用了数据加权平均技术,有效抑制了在实际制造过程中因反馈电容的非线性失配所产生的谐波。调制器基于SMIC 180 nm工艺设计,在1.8 V电源电压、3.072 MHz采样时钟频率、64倍过采样率、24 kHz信号带宽条件下,后仿真达到了102.7 dB的SNDR以及106 dB的动态范围(DR),调制器功耗为1.6 mW,FoMSNDR为174.5 dB,FoMDR为177.8 dB。在小幅度信号输入情况下,开启PGA后,额外消耗1.69 mW功耗,信噪失真比至多可提高5.93 dB。

       

      Abstract: A high-precision Delta-Sigma modulator tailored for audio codecs is introduced in this paper. It adopts a CIFF architecture characterized by a high input dynamic range. The loop filter is configured as a third-order single-loop structure, integrated with a 4-bit quantizer to mitigate the overload probability of switched-capacitor integrators in high-order systems and simultaneously elevate the Signal-to-Noise and Distortion Ratio (SNDR). A Programmable Gain Amplifier (PGA) serves as the input stage of the Delta-Sigma modulator, amplifying input signals in scenarios of low-amplitude inputs to broaden the modulator's dynamic range. Additionally, Data Weighted Averaging (DWA) technology is implemented to effectively suppress harmonics arising from nonlinear mismatches in feedback capacitors during manufacturing. Fabricated based on the SMIC 180 nm process, the modulator achieves an SNDR of 102.7 dB and a Dynamic Range (DR) of 106 dB in post-simulation under conditions of a 1.8 V power supply voltage, a 3.072 MHz sampling clock frequency, a 64-times oversampling rate, and a 24 kHz signal bandwidth. The modulator consumes 1.6 mW of power and exhibits a FoMSNDR of 174.5 dB and a FoMDR of 177.8 dB. When dealing with low-amplitude inputs and with the PGA enable, an extra 1.69 mW of power is consumed, potentially boosting the SNDR by up to 5.93 dB.

       

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