Abstract: This paper focuses on the design of a Digital Delay-locked Loop (DDLL) and its fault tolerance to Single Event Upsets (SEU), proposing a circuit-level SEU simulation method. First, the paper introduces a delay-line-based digital delay-locked loop. Then, it explores the generation and phenomena of SEU effects, simulating the effect by flipping node levels using switch capacitors. Next, it proposes reinforcement methods for different modules, adding redundant delay lines with voters to suppress SEU impacts, and designing dual-modular redundancy with dual-input inverters in TSPC flip-flops to enhance SEU resistance. To improve system stability, a lock recovery mechanism is designed for quick lock restoration after SEUs. Simulation results show that the designed DDLL operates at frequencies from 200 MHz to 600 MHz, with lock times ranging from 123.785 6 ns to 872.450 5 ns before reinforcement, and from 117.524 8 ns to 849.597 3 ns after. The fault-tolerant design effectively suppresses SEU-induced signal errors, providing effective solutions for delay-locked loop circuit design in radiation environments.