Abstract: As integrated circuit technology nodes continue to scale down, low-power design has become a central challenge in chip design. Although conventional power-gating techniques can effectively reduce static power consumption, their single-chain structure tends to generate excessively large inrush current during power-up, leading to significant IR drop and consequently increasing the risk of power-up failure. To address this issue, this paper proposes a dual-chain power-gating structure design and systematically compares and analyzes the power-up transient characteristics and inrush current behavior of both single-chain and dual-chain structures under identical process, voltage, and temperature conditions. Simulation results demonstrate that the dual-chain structure reduces the inrush current from 335.269 mA in the single-chain structure to 116.871 mA, representing a reduction of 65.2%, effectively suppressing the IR drop magnitude and significantly lowering the probability of power-up failure. This scheme provides a feasible engineering solution for low-power, high-stability integrated circuit design.