Abstract: Instract: Within the conventional von Neumann computer architecture, algorithms such as Convolutional Neural Networks, matrix operations, and Fast Fourier Transforms exhibit frequent data reuse, which results in numerous read-after-write instructions in vector processor pipelines and is prone to data hazards. Additionally, repeated data transfers between vector registers and computational units incur substantial power consumption overheads. To address these issues, a data hazard resolution mechanism tailored for vector computing is proposed. By leveraging data reuse to minimize data movement, the power consumption of the computing chip is effectively reduced. Simulation experiments applying this method to a RISC-V vector processor demonstrate that, during 128×128 matrix multiplication, overall chip power consumption is reduced by approximately 5.8%, and when computing neural convolutional network algorithms, power consumption is reduced by about 6.2%. The proposed approach features a lightweight design, with negligible area overhead introduced.