Abstract: Channel mismatch, primarily time skew, induced by process variations and random material property fluctuations in Time-Interleaved Analog-to-Digital Converters (TI ADCs) severely degrades overall conversion performance. To address this issue, a pure digital background calibration algorithm based on the Pearson correlation coefficient is proposed. The proposed algorithm eliminates the need for additional reference channels, thereby reducing analog area and power consumption. By avoiding complex derivative calculations during mismatch detection and employing a simplified computation method for compensation, the algorithm achieves high accuracy while minimizing computational complexity and power overhead. Furthermore, a novel multi-channel calibration logic is introduced to ensure robust performance in multi-channel applications. A 16-channel TI ADC, comprising 8-bit 62.5 MS/s Successive Approximation Register (SAR) ADCs designed in a SMIC 40 nm CMOS process, is utilized to verify the algorithm through simulation. Results demonstrate superior clock skew detection sensitivity and calibration effectiveness compared to conventional digital background calibration techniques. Experimental measurements further validate the efficacy, showing that the algorithm improves the Effective Number of Bits (ENOB) of a two-channel TI ADC from 4.5 bits to 7.3 bits, with the Signal-to-Noise and Distortion Ratio (SNDR) increasing from 28.8 dB to 45.9 dB.