Abstract: In computing-in-memory (CIM) systems, analog-to-digital converters (ADCs) are typically deployed in array configurations. Device mismatches, however, introduce offset voltages in the comparators within ADCs, leading to errors in matrix operations and consequently degrading the overall performance of the CIM system. Conventional offset calibration methods are predominantly designed for individual comparators and are often unsuitable for array applications due to their substantial area overhead and complex calibration circuitry. To address this issue, a low-area comparator offset calibration circuit tailored for CIM systems is proposed. The proposed scheme utilizes a 6-bit digital-to-analog converter (DAC) to generate a global calibration voltage, which is then integrated by a fully differential integrator. A binary search algorithm is employed to rapidly determine the required calibration voltage for each comparator, enabling precise offset voltage adjustment. Simulation results based on a 55 nm CMOS process demonstrate that, under a 20 MHz input clock, the comparator offset voltage is reduced from 14.7 mV (3.3σ) to 1.03 mV (3.3σ). The layout area of a single comparator with integrated calibration circuitry is 434 μm². Compared to conventional calibration approaches, the proposed method shares the calibration signal generation circuit and only requires an additional integrator per comparator, thereby eliminating complex calibration logic and significantly reducing the area overhead. This makes it particularly suitable for efficient calibration of comparator arrays.