Abstract: To address the critical demands for throughput enhancement and burst traffic absorption in low-earth-orbit (LEO) satellite data switching systems, this paper proposes a two-level arbitration with partitioned cache switching architecture. The architecture employs a hierarchical arbitration strategy to optimize multi-port parallel access, effectively alleviating the throughput bottleneck caused by resource-sharing conflicts. The system integrates a dynamic memory management mechanism, supports full-duplex store-and-forward operations across 16 Gigabit Ethernet ports, and incorporates an ECC checking unit with 2-bit error detection and 1-bit error correction capability, along with a multi-priority QoS scheduling algorithm to enhance data transmission reliability and service quality assurance. RTL-level design, synthesis, implementation, and system testing are completed on the Xilinx XC7V690T FPGA platform. Experimental results demonstrate that at an operating frequency of 156.25 MHz, the system achieves an average port line rate of 4 Gbps, with a total system throughput of 64 Gbps and a timing margin exceeding 20%. The proposed architecture achieves a favorable balance among throughput performance, timing closure, and hardware resource overhead, providing a valuable reference for the design and optimization of spaceborne switching systems.