Abstract: To address the drawbacks of traditional analog adaptive CTLE(Continuous Time Lineqar Equalizer), such as high sensitivity to PVT variations, and the excessive hardware overhead and long adaptation time of digital adaptive CTLE, a fast adaptive CTLE for the MIPI D-PHY high-speed interface at a data rate of 6 Gbps is proposed. According to the MIPI D-PHY specification, the interface features synchronized DDR sampling clock channels. this CTLE determines the optimal equalization parameters by setting different reference voltages and comparing the reference voltage at the sampling instant with the voltage of the equalized data signal. A binary search algorithm is introduced to reduce the adaptation time. The circuit is designed in TSMC 65 nm CMOS process with a 1.2 V supply voltage and a data rate of 6 Gbps. Simulation results show that the circuit can adaptively compensate for channel loss of 0 - 15 dB at 3 GHz, with an adaptation time of 32 microseconds. The equalized eye diagram meets the MIPI D-PHY 3.0 specification. This circuit features a short adaptation time, small area occupancy, and a simple optimization algorithm, providing a new option for MIPI D-PHY dedicated CTLE designs.