Abstract: The dual-transistor (2T0C) gain-cell memory based on the vertically Channel-All-Around (CAA) AmorphousOxide Semiconductor Field-effect Transistors (AOSFET) has attracted much attention due to its high carrier mobility, high storage density, low read power consumption, and potential for three-dimensional multi-layer stacking. However, in the crossbar storage array, the bypass crosstalk current severely restricts the read margin of the 2T0C storage array. Different application scenarios have differential requirements for the Signal-to-noise Ratio of crosstalk(SNRc) of the read current. Traditional solutions often need to increase the array read voltage or reduce the array size to ensure read reliability. Unlike silicon-based devices, AOSFET supports flexible regulation of the transistor threshold voltage (V_TH) through various processes. This paper proposes a read transistor V_TH optimization strategy for 2T0C arrays, which effectively suppresses bypass crosstalk by lowering the preset threshold voltage, reduces the working voltage of the storage array, and improves the column length and read margin. Furthermore, a method for selecting the read transistor threshold voltage for different application requirements is established, taking into account read speed and energy consumption. Simulation results show that when V_TH is set to -0.35V, the 64-unit storage column can achieve SNRc > 20 dB at a voltage of 0.775V, with a power consumption of only 15.12 fJ.