Abstract: The back-hopping effect of magnetic tunnel junctions (MTJs) exhibits high thermal stability and fast switching characteristics, making it one of the ideal p-bit devices for probabilistic computing. However, the symmetry of the transfer characteristic curves and device uniformity of current MTJ-based back-hopping p-bits still fall short of the requirements for large-scale probabilistic circuits (p-circuits). To address this issue, a method combining a lookup table module and two's complement arithmetic circuit is proposed. By applying a half-wave symmetric extrapolation technique, the transfer characteristic curves of MTJ devices under high bias can be effectively corrected, significantly improving p-bit accuracy. The proposed scheme is validated on a field-programmable gate array (FPGA), and the results show that the output probability distributions of the optimized basic logic gate circuits align well with theoretical expectations, with the KL divergence of the AND gate reduced to 0.048%. Experimental verification using two cascaded AND gates demonstrates that the system-level Hamiltonian exhibits a linear superposition property consistent with the Hamiltonians of the basic logic gates. Moreover, by adjusting parameter configurations, a configurable true random number generator (TRNG) is implemented, supporting multiple output distributions such as normal, chi-squared, and uniform distributions. For resource optimization in multi-p-bit systems, a time-division multiplexing strategy based on sequential updates is proposed. By increasing control logic to reuse a single p-bit module, this approach reduces the resource consumption of lookup tables and D flip-flops by over 80% while maintaining processing speed.