Abstract: To address the capacitor mismatch problem in Successive Approximation Register Analog-to-Digital Converters (SAR ADCs), a foreground digital calibration algorithm for a 12 bit SAR ADC is proposed, along with the design of a column-parallel SAR ADC suitable for this algorithm. The proposed algorithm offers advantages such as fast convergence, high stability, and low circuit overhead. It effectively compensates for capacitor mismatches in column-level readout circuits of SAR ADCs, thereby enabling the application of SAR ADCs in the column-level readout of CMOS image sensors (CMOS Image Sensor, CIS) for high-frame-rate CIS chip design. Key innovations include: A sub-radix capacitor array ensuring correctability of each output code. The maximum radix is calculated and a segmented capacitor array with 2 bit redundancy is designed to minimize area. Utilizing multi-channel parallel column ADC output averages as reference signals, achieving high-precision references without additional circuitry. A momentum-enhanced least mean square (LMS) algorithm that optimizes iteration direction beyond local optima, combined with a novel step-size update formula improving stability. This achieves over 10 times faster convergence. Implemented in SMIC 0.18 μm CMOS technology, the design incorporates capacitor mismatch from Monte Carlo simulations during post-layout verification. After 500 iterations, actual capacitor weights are calibrated. At 1 MS/s sampling rate: SNDR improves from 57.9 dB (mismatched) to 68.6 dB (calibrated), INL/DNL reduce from −1 - 2 LSB to −0.5 - +0.5 LSB, occupies 0.0499 mm² with 149 μW power consumption. The solution demonstrates an area-efficient, low-power approach for high-precision CIS readout systems.