Abstract: To address the limitation of effective number of bits (ENOB) improvement in noise-shaping successive approximation register (SAR) analog-to-digital converters (ADCs), a high-precision design scheme combining KT/C noise cancellation technology and a second-order cascaded integrator feedforward (CIFF) noise shaping structure is proposed. Conventional methods for enhancing SAR ADC precision mainly rely on increasing the order of noise shaping or using large capacitors to suppress thermal noise, which often leads to increased chip area, higher power consumption, and greater circuit complexity. The proposed method introduces dynamic thermal noise cancellation technology, which stores and cancels thermal noise during the sampling phase of the capacitive digital-to-analog converter (CDAC). Additionally, by integrating a passive charge-sharing mechanism and a parallel second-order CIFF structure, the proposed approach simultaneously suppresses quantization noise and KT/C noise, thereby improving ADC accuracy. Based on the 180 nm CMOS process, simulations were conducted at a sampling rate of 5 MHz with an oversampling ratio (OSR) of 16, demonstrating significant performance improvements. The results show that after applying KT/C noise cancellation technology, in-band thermal noise is significantly reduced, the signal-to-noise and distortion ratio (SNDR) increases from 87.9 dB to 100.5 dB, and the ENOB improves from 14.31 bits to 16.40 bits. Moreover, this method does not require a significant increase in chip area or power consumption, providing an efficient and feasible solution for high-precision SAR ADC design.