Abstract: The capacitorless dual-transistor (2T0C) gain cell (GC) technology, compatible with low-temperature processes and 3D integration, holds strong potential as a next-generation high-density, low-power memory. However, in large-scale 2T0C GC arrays, the write consistency of the storage charge (Q_SN) at the storage node (SN) significantly degrades due to variations in transistor parameters, interconnect parasitics, and coupling between adjacent cells. Memory channel modeling provides an effective approach to statistically characterize logical errors induced by physical disturbances during read and write operations. This paper proposes using a Binary Asymmetric Channel (BAC) model to describe the statistical characteristics of Q_SN writing in 2T0C gain cells. Based on this model, the noise probability distribution of written Q_SN induced by transistor electrical parameter fluctuations and channel carrier injection effects is investigated, and the differences in Q_SN writing due to write delays caused by interconnect parasitic parameters in large-scale arrays are analyzed. Furthermore, a Gaussian Mixture Model is employed to characterize the probability density distribution of Q_SN writing in large-scale 2T0C GC arrays. Comparison with circuit simulation results indicates that the proposed Gaussian Mixture Model can accurately predict the probability distribution of Q_SN writing when the noise disturbance is σ ≤ 7%.