Abstract: To address the issue of insufficient utilization of inherent sparsity in input activations within existing convolutional neural network (CNN) accelerator designs, this paper proposes a field-programmable gate array (FPGA)-based Processing Element (PE) design scheme for CNN accelerators. First, a hardware-implemented Sobel edge detection algorithm is employed to preprocess input images, effectively extracting key edge features and significantly enhancing the sparsity of input activations. Second, an improved sparse activation skipping mechanism is designed to fully exploit the sparsity characteristics of input activations, thereby improving system throughput while substantially reducing energy consumption. Furthermore, a multi-bank hybrid ping-pong read/write mechanism with one-write-multiple-read capability is proposed to optimize the storage scheme for input activations during convolution operations, achieving an optimal balance between area efficiency and throughput. To validate the effectiveness of the proposed scheme, a ResNet CNN is trained using the PyTorch framework and systematically evaluated on the CIFAR-10 and CIFAR-100 datasets. Experimental results demonstrate that the edge detection preprocessing does not significantly affect network classification accuracy. Performance evaluation reveals that, compared with the state-of-the-art designs, the proposed architecture achieves a 2.18× improvement in energy efficiency, an 84% increase in throughput per unit area, and a 42.9% reduction in power consumption per unit area, demonstrating significant advantages in both computational and energy efficiency. This study provides a novel technical pathway for the design of high-performance and low-power neural network accelerators, with broad application prospects.