Abstract: To address the requirements of performance evaluation and mass production testing for ultra-high-speed analog-to-digital converters (ADCs) with JESD204B interfaces, this paper proposes a JESD204B-based ultra-high-speed ADC test method utilizing automated test equipment (ATE). The proposed method achieves a maximum throughput of 200 Gbps on a single board while supporting system expansion, aiming to eliminate the dependence on FPGA programming in conventional testing, enhance test versatility and efficiency, and satisfy the demands of large-scale production and performance assessment. Through analysis of the performance testing requirements for ultra-high-speed ADCs, a low-jitter clock scheme that does not rely on an external high-precision signal source is designed, significantly reducing the clock jitter to 87 fs. At the physical layer, a 10B+20B trigger pattern is employed to locate critical data, and the trigger keywords are adjusted to overcome the data acquisition limitations of the ATE capture board, enabling synchronized acquisition and parsing of 16-lane 7.5-Gbps JESD204B data. The original ADC data are subsequently reconstructed through data recombination, thereby accomplishing comprehensive performance testing. The proposed method is validated on a 6-GSPS ADC with a JESD204B interface. Under a 4-GHz sinusoidal input, the measured signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) reach 52 dBFS and 65.8 dBFS, respectively. The clock jitter is reduced from 5 ps to 87 fs, representing an improvement of more than one order of magnitude, which effectively resolves the incompatibility of conventional ATE systems with the JESD204B protocol. The test results exceed the typical specifications of comparable devices and meet all design requirements. The entire development process involves no FPGA programming, and the ATE-based platform ensures excellent versatility, stability, and scalability, providing an efficient solution for engineering testing of ultra-high-speed ADCs.