Abstract: This paper presents and validates a digital circuit design scheme for a configurable low-power Σ-Δ digital-to-analog converter (DAC), which encompasses two core modules: a digital interpolation filter and a digital modulator. In the interpolation filter, a folding algorithm is employed to optimize the structures of the half-band filter and the finite impulse response (FIR) compensation filter, reducing both the multiplier and adder resources to one each, thereby significantly lowering hardware overhead. Under a system clock of 10.24 MHz, by flexibly configuring the interpolation factor of the CIC interpolation filter and the operating mode of the digital loop modulator according to the frequency of the input signal, four different effective bit resolutions—namely 10-bit, 12-bit, 14-bit, and 16-bit—can be achieved for digital signal output, catering to the performance requirements of diverse application scenarios. Fabricated in SMIC's 22-nm CMOS process, the completed layout occupies a core area of 131 μm × 131 μm and consumes a total power of only 0.215 1 mW, which verifies the superiority of the proposed architecture in terms of low power consumption and configurability.