Abstract: This paper presents a 16-bit 65-MS/s rail-to-rail pipeline analog-to-digital converter (ADC) implemented in a 0.18-μm CMOS process. To enhance the input dynamic range and quantization performance under high-speed and low-power operation, an improvement is proposed for the first-stage multiplying digital-to-analog converter (MDAC). By introducing an extra digital code to fold the transfer curve, the input signal range of the MDAC is doubled while maintaining the original output swing, thereby effectively improving the system's tolerance to large-amplitude input signals and enhancing the signal-to-noise ratio. To avoid the limitations imposed by rail-to-rail signals on the sample-and-hold circuit, a sample-and-hold amplifier (SHA)-free architecture is adopted. Furthermore, to meet the design requirements of high speed and high input swing, a gain-boosted two-stage operational amplifier with high bandwidth and high output swing is designed. Operating from a 1.8-V supply, the ADC is capable of handling a 3.6-Vpp differential input signal. Simulation results demonstrate that at a sampling rate of 65 MS/s and an input frequency of 5.078 MHz, the ADC achieves an effective number of bits (ENOB) of 13.57 bits, a signal-to-noise-and-distortion ratio (SNDR) of 83.4 dB, and a spurious-free dynamic range (SFDR) of 91.4 dB, while consuming a total power of 110 mW. These results verify the feasibility of the proposed architecture for high-speed and high-dynamic-range applications.