Abstract: With the development of quantum computer and quantum algorithms, quantum-resistant cryptography algorithms (also known as post-quantum cryptography algorithms) have been proposed to resist potential quantum attacks. However, at present, there is still relatively little research work on the hardware implementation and performance evaluation of the Lattice-based Asymmetric Cryptography (LAC) algorithm. This paper conducts a hardware evaluation of the LAC algorithm, proposes a number-theoretic transformation hardware structure adapted to small prime numbers of LAC, and a series of BCH decoding circuit modules. The total circuit has an area of 1.7 mm² based on the 28 nm process, and the key generation, sealing, and unsealing respectively reach 12561, 15614, and 21072 clock cycles, with a frequency of 500 MHz. To our knowledge, it is currently the only full hardware implementation for the LAC algorithm.