Abstract: To address the trade-off between energy efficiency and gain-bandwidth in high-speed high-resolution analog-to-digital converters, a 230 MS/s 14 bit Pipeline SAR ADC based on 28 nm CMOS process is presented. A dynamic bandwidth-enhanced ring amplifier replaces conventional static operational amplifiers to decouple gain-bandwidth performance from process-voltage-temperature (PVT) variations in the residue amplification stage. This amplifier incorporates a replica biasing branch, clamping loop and Floating-Inverter-Amplifier (FIA) to achieve self-stabilizing output common-mode voltage. Correlated Level Shifting (CLS) technology further enhances effective open-loop gain. Low-power asynchronous SAR logic and a high-speed dynamic comparator with multiple cross-coupled pairs accelerate sub-ADC conversion. Post-layout simulation results demonstrate that over the full temperature range of −55 °C to 125 °C and across various process corners, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) better than 70 dB at 230 MS/s, with a typical value of 72.45 dB. The prototype consumes 3.849 mW of power, achieving an energy efficiency of 4.89 fJ/conv-step and a figure of merit (FoM) of 177.2 dB. This design effectively overcomes the performance limitations of conventional architectures, providing an energy-efficient solution for high-speed high-resolution data conversion systems.