Abstract: A wide-tuning-range high performance digitally controlled oscillator (DCO) is proposed for clock recovery in high-speed SerDes system, achieving wide rate SerDes system data transmission across 1.25Gb/s~16 Gb/s. The design employs current-mode feed-forward architecture and utilizes sub-loops and auxiliary paths with current-steering logic to achieve 0.9 MHz frequency regulation resolution and ±1° phase adjustment. Fabricated in 28 nm CMOS process, the oscillator demonstrates 5.94 s⁻¹ output jitter at 6.25 GHz with 932 μW core power, while the complete system including current-mode control and power delivery consumes 4.71 mW. Integrated into a SerDes system, it enables error-free data transmission from 1.12Gb/s~16.5 Gb/s, maintaining excellent jitter performance and frequency adaptability across a 2.24GHz~8.25GHz frequency range.