Abstract: Herein, a successive approximation register analog-to-digital converter (SAR ADC) featuring 16-bit resolution and a 2 MS/s sampling rate is designed based on the 0.18 μm CMOS process. The ADC employs a fully differential structure and a V_cm-based switching scheme to effectively suppress common-mode noise, improve even-order harmonic distortion, while optimizing system power consumption and area. To address the capacitor mismatch issue caused by process variations in high-precision SAR ADCs, this work proposes a foreground digital self-calibration algorithm based on the charge-balance principle. The core innovation of this algorithm lies in reusing the capacitor array itself as the calibration tool, eliminating the need for additional analog calibration circuits. It achieves precise measurement of high-bit capacitor mismatch through this approach, and employs an iterative calibration methodology that utilizes the preliminarily calibrated high-bit capacitor array to remeasure and correct the mismatch errors in the low-bit calibration DAC itself, thereby systematically resolving the error propagation bottleneck inherent in traditional calibration schemes due to inaccuracies in the calibration DAC. To validate the effectiveness of the proposed architecture and calibration algorithm, comprehensive simulation verification is conducted. Simulation results demonstrate that with an introduced capacitor mismatch of 0.5%, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 65.5 dB to 87.3 dB, and the effective number of bits (ENOB) increases from 10.59 bit to 14.21 bit after calibration, while other key figures of merit such as spurious-free dynamic range (SFDR) are also significantly enhanced. The results confirm that the proposed self-calibration method effectively overcomes the nonlinearity arising from capacitor mismatch and substantially restores both the static linearity and dynamic performance of the ADC.