Abstract: Compute-in-Memory (CIM) technology can reduce data movement, alleviating the“memory wall” bottleneck inherent to the von Neumann architecture. Among various implementations, embedded Dynamic Random-access Memory (eDRAM) based on Amorphous Oxide Semiconductor Field-effect Transistors (AOSFETs) is particularly attractive for constructing large-scale analog CIM arrays due to its high integration density. Compared with the conventional two-transistor zero-capacitor (2T0C) cell, the three-transistor zero-capacitor (3T0C) cell significantly improves the linearity of CIM outputs by strongly suppressing sneak currents in crossbar arrays and eliminating the feedback path formed by the coupling capacitance between the read word line and the bit line. However, limited by the read bit-line capacitance, the 3T0C scheme still suffers from severe linearity degradation under high read-current conditions, such as multi-row parallel readout or elevated operating temperatures. To address this issue, this paper proposes a Cascaded Current Mirror (CCM) output stage added to the read bit line of the 3T0C array. With a low hardware overhead of only four transistors per column, the proposed design decouples the read current from the voltage swing by clamping the read bit-line voltage, while the mirror ratio is exploited to regulate and amplify the equivalent load capacitance. Simulation results on a 256×64 array show that, at room temperature and 80°C, the proposed design achieves an integral nonlinearity (INL) of less than one least significant bit (LSB) during four-row parallel readout, improving the INL by 70% and 83.8%, respectively, compared to the 3T0C scheme without the CCM.